? semiconductor components industries, llc, 2001 february, 2001 rev.0 1 publication order number: an8044/d and8044/d single-channel 1206a chipfet power mosfet recommended pad pattern and thermal performance introduction new on semiconductor chipfets in the leadless 1206a package feature the same outline as popular 1206a resistors and capacitors but provide all the performance of true power semiconductor devices. the 1206a chipfet has the same footprint as the body of the tsop6 and can be thought of as a leadless tsop6 for purposes of visualizing board area, but its thermal performance bears comparison with the much large so8. this technical note discusses the singlechannel chipfet 1206a pinout, package outline, pad patterns, evaluation board layout and thermal performance. pinout figure 1 shows the pinout description and pin 1 identification for the singlechannel 1206a chipfet device. the pinout is similar to the tsop6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. the legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. figure 1. single 1206a chipfet style 1: pin 1. drain 2. drain 3. drain 4. gate 5. source 6. drain 7. drain 8. drain 1 8 basic pad patterns the basic pad layout with dimensions is shown in figure 2. this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. the minimum recommended pad pattern, shown in figure 3, improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0054 sq. in. or 3.51 sq. mm. this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. an example of this method is implemented on the evaluation board described in the next section (figure 4). figure 2. basic pad layout figure 3. minimum recommended pad pattern 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 26 mil 28 mil 80 mil 68 mil 28 mil 80 mil 25 mil 26 mil 18 mil http://onsemi.com application note
and8044/d http://onsemi.com 2 evaluation board for the single 1206a the chipfet 1206a evaluation board measures 0.6 in by 0.5 in. its copper pad pattern consists of an increased pad area around the six drain leads on the topside approximately 0.0482 sq. in. 31.1 sq. mm and vias added through to the underside of the board, again with a maximized copper pad area of approximately the boardsize dimensions. the outer package outline is for the 8pin dip, which will allow test sockets to be used to assist in testing. the thermal performance of the 1206a on this board has been measured with the results following on the next page. the testing included comparison with the minimum recommended footprint on the evaluation boardsize pcb and the industry standard oneinch square fr4 pcb with copper on both sides of the board. figure 4. evaluation board 1206a chipfet ? d d d g d d d s front of board back of board rev. a chipfet thermal performance junctiontofoot thermal resistance (the package performance) thermal performance for the 1206a chipfet measured as junctiontofoot thermal resistance is 15 c/w typical, 20 c/w maximum for the single device. the afooto is the drain lead of the device as it connects with the body. this is identical to the so8 package r q jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. junctiontoambient thermal resistance (dependent on pcb size) the r q ja typical for the singlechannel 1206a chipfet is 80 c/w steady state, compared with 68 c/w for the so8. maximum ratings are 95 c/w for the 12068 versus 80 c/w for the so8. testing to aid comparison further, figure 5 illustrates chipfet 1206a thermal performance on two different board sizes and three different pad patterns. the results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. the measured steady state values of r q ja for the single 1206a chipfet are: ????????????? ? ???????????? ????????????? minimum recommended pad pattern (see figure 3) on the evaluation board size of 0.5 in. x 0.6 in. ??? ?? ? ??? 156 c/w ????????????? ????????????? the evaluation board with the pad pattern described on figure 4 ??? ??? 111 c/w ????????????? ? ???????????? ????????????? industry standard 1 square pcb with maximum copper both sides. ??? ?? ? ??? 78 c/w the results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. in this example, a 45 c/w reduction was achieved without having to increase the size of the board. if increasing board size is an option, a further 33 c/w reduction was obtained by maximizing the copper from the drain on the larger 1 square pcb.
and8044/d http://onsemi.com 3 10 5 120 10 2 10 3 10 4 thermal resistance (c/w) 0 figure 5. single 1206a chipfet 160 single evb min. footprint time (secs) 40 80 10 1 1 10 100 1000 1o square pcb summary the thermal results for the singlechannel 1206a chipfet package display similar power dissipation performance to the so8 with a footprint reduction of 80%. careful design of the package has allowed for this performance to be achieved. the short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the tsop6 body size.
and8044/d http://onsemi.com 4 package dimensions chipfet case 1206a02 issue b b s c d g l a 1234 8765 m j k 1 2 3 4 8 7 6 5 dim min max min max inches millimeters a 2.95 3.10 0.116 0.122 b 1.55 1.70 0.061 0.067 c 1.00 1.10 0.039 0.043 d 0.25 0.35 0.010 0.014 g 0.65 bsc 0.025 bsc j 0.10 0.20 0.004 0.008 k 0.28 0.42 0.011 0.017 l 0.55 bsc 0.022 bsc m 5 nom s 1.90 bsc 0.076 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 7. 126a-01 obsolete. new standard is 1206a-02. 0.05 (0.002) 5 nom on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8044/d chipfet is a trademark of vishay siliconix. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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